One of the primary steps in the fabrication of modern semiconductor devices is the formation of an electrically insulating film on a semiconductor substrate. Such insulating films are used for a variety of purposes. For example, in some instances adjacent conductive layers may be separated, such as where an intermetal dielectric (“IMD”) layer is used to separate adjacent metal lines or where a premetal dielectric (“PMD”) layer is used to separate a metal layer from the conductive substrate. In other instances, adjacent active regions of the substrate may be separate, such as in shallow-trench-isolation (“STI”) structures.
For processes in which IMD or PMD layers are formed in an integrated circuit, or for processes used in the formation of STI structures, it is typically necessary to fill gaps defined between adjacent structures. For example, FIG. 1 provides a simplified cross-sectional view of a partially completed integrated circuit 100. This integrated circuit is formed over a substrate 104 that includes a plurality of STI structures, each of which is typically created by forming a thin pad oxide layer 120 over the surface of the substrate 104 and then forming a silicon nitride layer 116 over the pad oxide layer 120. The nitride and oxide layers are then patterned using standard photolithography techniques and trenches 124 are etched through the nitride/oxide stack into the substrate 104. FIG. 1 shows that the integrated circuit may comprise areas 108 that are relatively densely packed with transistors or other active devices, and may comprise open areas 112 that are relatively isolated. Active devices in the open areas 112 may be separated from each other by more than an order of magnitude than separations in the densely packed areas 108.
Subsequently, the trenches 124 are filled with an electrically insulating material such as silicon dioxide using a deposition process that has good gapfill properties. Examples of such techniques include plasma deposition processes, such as plasma-enhanced chemical-vapor deposition (“PECVD”) and high-density-plasma chemical-vapor deposition (“HDP-CVD”), as well as thermal chemical-vapor deposition (“CVD”) processes. In some instances, prior to the gapfill process, an initial lining layer is deposited over the substrate as an in situ steam generation (“ISSG”) or other thermal oxide layer, or perhaps a silicon nitride layer. One benefit to depositing such a liner prior to filling the trenches 124 is to provide appropriate corner rounding, which may aid in avoiding such effects as early gate breakdown in transistors that are formed. In addition, such a liner may aid in relieving stress after the CVD deposition.
While this technique has had good success in applications having relatively high thermal budgets, it is not compatible with applications in which thermal budgets are more restrictive. For instance, a recent trend towards the use of materials that impose more restrictive thermal budgets is exemplified by the use of strained silicon components instead of more conventional unstrained materials. Strained silicon is increasingly advocated for use in device channels as a mechanism for enhancing channel mobility, and is expected to dominate high-performance devices having feature sizes of 65 nm or less. The biaxial tensile stress that provides strained silicon with its desirable properties is, however, destroyed when the material is subjected to the high temperatures used in the process described above.
There is, accordingly, a general need in the art for approaches to filling gaps that meet lower thermal budgets.